1) Field of the Invention
The present invention relates to a semiconductor device, a display device, and a signal transmission system. In particular, the present invention relates to a semiconductor device which is cascade-connected and processes signals, and a display device and a signal transmission system which include a cascade connection and processes signals.
2) Description of the Related Art
For example, in liquid crystal display (LCD) devices, pixels each including a transistor are arranged in rows and columns, gate bus lines extending in the horizontal direction are connected to gates of the transistors in the pixels, and data bus lines extending in the vertical direction are connected to capacitors in the pixels through the transistors. When data is displayed on an LCD panel, a gate driver sequentially drives each gate bus line on a line-by-line basis so as to bring transistors connected to the gate bus line into conduction, and then data drivers simultaneously write data into pixels on the line in the horizontal direction through the conducting transistors.
In the conventional constructions, LCD drivers are commonly connected to buses which propagate display-data signals, a clock signal, and the like. In such constructions, signal wires intersect, and therefore the number of mounted circuit board layers becomes great. In order to decrease the number of mounted circuit board layers, the LCD drivers are cascade-connected so that outputs of each LCD driver are supplied to another LCD driver in the following stage.
Since LCD drivers are connected in series in the cascade connection, mounted signal wires do not intersect, and therefore the number of mounted circuit board layers can be decreased. Thus, the circuit boards can be manufactured at low cost.
FIG. 9 is a diagram illustrating an example of a conventional LCD device having a cascade-connected construction. The LCD device of FIG. 9 comprises an LCD panel 10, a control circuit 11, a gate driver 12, data driver ICs 13, and signal lines 15.
In the LCD panel 10, pixels each including a transistor (not shown) are arranged in rows and columns, gate bus lines extending from the gate driver 12 in the horizontal direction are connected to gates of the transistors in the pixels, and data bus lines extending from the data driver ICs 13 in the vertical direction are connected to capacitors in the pixels through the transistors. When data is displayed on the LCD panel 10, the gate driver 12 sequentially drives each gate bus line on a line-by-line basis so as to bring transistors connected to the gate bus line into conduction, and then the data driver ICs 13 simultaneously write data through the conducting transistors into pixels on each horizontal line in the horizontal direction.
The control circuit 11 is a circuit which controls the gate driver 12 and the data driver ICs 13 so as to display data on the LCD panel 10. Signals outputted from the control circuit 11 are first supplied to the data driver ICs 13 in the first stage, and are then supplied from a data driver IC 13 in each stage to another data driver IC 13 in the following stage.
The gate driver 12 sequentially drives each gate bus line on a line-by-line basis under the control of the control circuit 11 so as to bring transistors connected to the gate bus line into conduction.
The data driver ICs 13 are cascade-connected, and latch data which are supplied from the control circuit 11 and are to be displayed, in synchronization with a clock signal. The data latched by each data driver IC 13 are supplied to the LCD panel 10 and the next data driver IC 13.
FIG. 10 is a diagram illustrating details of an example of each of the data driver ICs 13. The data driver IC 13 illustrated in FIG. 10 comprises input buffers 20 to 23, a counter 24, a clock control circuit 25, a data control circuit 26, a latch circuit 27, and output buffers 28 to 31.
A start signal (START) is inputted into the input buffer 20, the clock signal (CLOCK) is inputted into the input buffer 21, a reset signal (RESET) is inputted into the input buffer 22, and a data signal (DATA) is inputted into the input buffer 23.
The counter 24 counts clock cycles of the clock signal outputted from the clock control circuit 25. When the count reaches a predetermined value, the counter 24 activates a start signal supplied to the output buffer 28.
The clock control circuit 25 controls the counter 24, the data control circuit 26, and the latch circuit 27 in response to the clock signal supplied from the input buffer 21, the start signal, and the reset signal, and supplies the clock signal to the output buffer 29.
The data control circuit 26 latches the data signal inputted through the input buffer 23, in synchronization with the clock signal supplied from the clock control circuit 25, and supplies the latched data signal to the latch circuit 27.
The latch circuit 27 latches the data signals supplied from the data control circuit 26, and supplies the latched data signals to the LCD panel 10.
The output buffer 28 supplies the start signal outputted from the counter 24, to the next data driver IC 13.
The output buffer 29 supplies the clock signal outputted from the clock control circuit 25, to the next data driver IC 13.
The output buffer 30 supplies the reset signal outputted from the input buffer 22, to the next data driver IC 13.
The output buffer 31 supplies the data signal outputted from the data control circuit 26, to the next data driver IC 13.
FIG. 11 is a diagram illustrating details of an example of the data control circuit 26. In the example of FIG. 11, the data control circuit 26 is comprised of an input circuit 40 and an output circuit 44. The data control circuit 26 latches a data signal in synchronization with a leading edge and a trailing edge of the clock signal, supplies the latched data signals to the LCD panel 10, synthesizes the latched data signals so as to reproduce the data signal, and outputs the synthesized data signal.
The input circuit 40 is comprised of an inverter 41 and data flip-flop (DFF) circuits 42 and 43. The DFF 42 latches the data signal in synchronization with a trailing edge of the clock signal, and the DFF 43 latches the data signal in synchronization with a leading edge of the clock signal. The data signals latched by the DFFs 42 and 43 are supplied to the latch circuit 27 and the output circuit 44.
The output circuit 44 is comprised of inverters 45 and 46 and NAND gates 47 to 49, synthesizes the data signals latched by the DFFs 42 and 43 in synchronization with the clock signal, and outputs the synthesized data signal.
FIG. 12 is a diagram illustrating details of an example of the counter 24. The counter 24 is realized by a shift register constituted by DFFs 50-1 to 50-n and 51 and an inverter 52, where the number of the DFFs 50-1 to 50-n and 51 corresponds to the number n+1 of clock cycles which are necessary for capture of the data signal. The counter 24 has a function of notifying an IC in the following stage of start timing of capture of a clock signal and a data signal supplied from the stage in which the counter 24 is arranged.
Next, the operations of the above conventional example are explained.
When an image signal is inputted into the control circuit 11, the control circuit 11 outputs a reset signal to be supplied to the data drivers IC 13 in the first stage.
Each of the data driver ICs 13 reads in the reset signal through the input buffer 22, and resets the clock control circuit 25 and the counter 24. Thereafter, each of the data driver ICs 13 supplies the reset signal to another data driver IC 13 in the next stage. Consequently, the data driver ICs 13 are reset one after another.
Subsequently, when a clock signal and a data signal are outputted from the control circuit 11, the data driver IC 13 in the first stage reads in the clock signal and the data signal through the input buffer 21 and the input buffer 23 (see FIG. 13. (A) and (B)), and supplies the clock signal and the data signal to the clock control circuit 25 and the data control circuit 26, respectively.
When a start signal is inputted, the DFF 43 in the data control circuit 26 latches the data signal in synchronization with a leading edge of the clock signal, and outputs the latched data signal as a signal A (see FIG. 13, (C)) to the latch circuit 27. On the other hand, the DFF 42 in the data control circuit 26 latches the data signal in synchronization with a trailing edge of the clock signal, and outputs the latched data signal as a signal B (see FIG. 13, (D)) to the latch circuit 27.
The latch circuit 27 latches the data supplied from the data control circuit 26, and supplies the latched data to the LCD panel 10.
After the counter 24 is reset with the reset signal, the counter 24 counts clock cycles of the clock signal. When (n−1)+0.5 cycles of the clock signal elapse, the counter 24 sets the start signal supplied to the output buffer 28, to the “H” state.
The output buffer 29 and the output buffer 31 respectively output the clock signal and the data signal to the next data driver IC 13 (see FIG. 13, (E) and (F)).
As explained above, the data signal outputted from the control circuit 11 is sequentially latched by the data driver ICs 13 in synchronization with the clock signal, and the latched data signals are then supplied to the LCD panel 10.
The gate driver 12 drives each of predetermined gate bus lines on the LCD panel 10 so as to bring transistors on each line into conduction. Thus, data supplied from the data driver ICs 13 are displayed on predetermined lines on the LCD panel 10.
However, in the case where the data driver ICs 13 are cascade-connected, when a signal is inputted into a driver device, the signal is supplied through an output buffer to a driver device in the next stage. At this time, there is a difference in the signal delay in the buffer between a leading edge and a trailing edge of the signal, where the difference is caused by manufacturing processes. Therefore, the duty ratio of the signal at the output stage is slightly different from the duty ratio of the signal at the input stage.
In the case where the data driver ICs 13 having similar delay characteristics are cascade-connected, errors of the duty ratio of a signal which are produced when the signal passes through the respective data driver ICs 13 are accumulated. Therefore, sometimes, the accumulated error of the duty ratio of the signal after the signal passes through the drivers in multiple stages becomes unignorable. For example, in SXGA (Super Extended Graphics Array) LCD panels, ten data driver ICs 13 are cascade-connected. Therefore, there is a possibility that normal shapes of signals cannot be maintained during propagation of the signals through the ten data driver ICs 13 due to the accumulated error in the duty ratio.
FIG. 14 is a diagram illustrating waveforms of the clock signal at the input stages of ten, cascade-connected, data driver ICs 13. As illustrated by reference (A) in FIG. 14, the clock signal has a rectangular shape when the signal is inputted into the first data driver IC 13. However, every time the clock signal passes through a data driver IC 13, the duration of the “H” state is elongated, and the duration of the “L” state is shortened.
That is, the duty ratio of the clock signal varies from the duty ratio of the waveform at the time of input into the first data driver IC 13. Therefore, some data driver IC 13 may not normally operate.
Thus, in Japanese Patent Application No. 2002-19518, the present inventors have proposed an integrated circuit in which errors of the duty ratio are not accumulated by inverting the output of the clock signal at each data driver IC 13.
FIG. 15 is a diagram illustrating details of the LCD device proposed by the above Japanese patent application No. 2002-19518. As illustrated in FIG. 15, the integrated circuit disclosed in the above Japanese patent application comprises an LCD panel 10, a control circuit 11, a gate driver 12, and data driver ICs 16. When compared with the construction of FIG. 9, the data driver ICs 13 are replaced with the data driver ICs 16. As a odd-even switch signal, a GND signal is inputted into each of the odd-numbered ICs, and a VDD signal is inputted into each of the even-numbered ICs. The other portions of the construction of FIG. 15 are identical to FIG. 9.
FIG. 16 is a diagram illustrating details of a construction of each data driver IC 16 in the construction of FIG. 15. The data driver IC 16 of FIG. 16 comprises input buffers 60 to 62, an inverter 63, a signal-inversion switch circuit 64, a clock controller 65, a data controller 66, an internal circuit 67, an inverter 68, a signal-inversion switch circuit 69, an inverter 70, and output buffers 71 and 72.
Next, the operations of the device disclosed in the above Japanese patent application No. 2002-19518 are briefly explained.
Since a GND signal or a VDD signal is inputted into the input buffer 62 according to the position of each data driver IC 16 in the cascade connection, each of the signal-inversion switch circuits 64 and 69 selects one of two terminals according to the state of the signal inputted through the input buffer 62.
FIG. 17 is a diagram illustrating the connection state in each of the odd-numbered data driver ICs 16 in the cascade connection. Since the GND signal is inputted as an odd-even switch signal into each of the odd-numbered data driver ICs 16, the signal-inversion switch circuit 64 selects the output of the input buffer 60, and the signal-inversion switch circuit 69 selects the output of the inverter 68, as illustrated in FIG. 17.
FIG. 18 is a diagram illustrating the connection state in each of the even-numbered data driver ICs 16 in the cascade connection. Since a VDD signal is inputted as an odd-even switch signal into each of the even-numbered data driver ICs 16, the signal-inversion switch circuit 64 selects the output of the inverter 63, and the signal-inversion switch circuit 69 selects the output of the clock controller 65, as illustrated in FIG. 18.
Therefore, the clock signal inputted into each of the odd-numbered data driver ICs 16 is supplied as is to the clock controller 65, and is thereafter inverted by the inverter 68. Then, the output of the inverter 68 is output from the data driver IC 16.
On the other hand, the clock signal inputted into each of the even-numbered data driver ICs 16 is inverted by the inverter 63, and is then supplied to the clock controller 65. Thereafter, the inverted clock signal is output as is from the data driver IC 16.
Consequently, even if the duration of the “H” state of the clock signal is elongated, the clock signal is inverted when the clock signal passes through the clock controller 65 in each data driver IC 16, as illustrated in FIG. 19. Therefore, the errors of the duty ratio of the clock signal are canceled. Thus, it is possible to prevent accumulation of the errors of the duty ratio during propagation through the plurality of data driver ICs 16.
However, since a GND signal or a VDD signal is required to be supplied to each data driver IC 16, the construction of the device is complex.